Test WRR+2W+poar+dmb+A

ARM WRR+2W+poar+dmb+A
"RfeAA PodRRAR FreRNa DMBdWW WseNaA"
Cycle=RfeAA PodRRAR FreRNa DMBdWW WseNaA
Prefetch=1:x=F,1:y=T,2:y=F,2:x=W
Com=Rf Fr Ws
Orig=RfeAA PodRRAR FreRNa DMBdWW WseNaA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x;
}
 P0                  | P1                 | P2           ;
 MOV %T3,#2          | LDREX R0,[%x1]     | MOV R0,#1    ;
 LDREX R0,[%x0]      | STREX %T2,R0,[%x1] | STR R0,[%y2] ;
 STREX %T2,%T3,[%x0] | CMP %T2,#0         | DMB          ;
 CMP %T2,#0          | BNE Fail1          | MOV R1,#1    ;
 BNE Fail0           | LDREX R1,[%y1]     | STR R1,[%x2] ;
 B Exit0             | B Exit1            |              ;
 Fail0:              | Fail1:             |              ;
 MOV R1,#0           | MOV R2,#0          |              ;
 STR R1,[%ok0]       | STR R2,[%ok1]      |              ;
 Exit0:              | Exit1:             |              ;
Observed
    0:R0=0; 1:R0=1; 1:R1=0; ok=1; x=1;
and 0:R0=1; 1:R0=1; 1:R1=0; ok=1; x=2;
and 0:R0=1; 1:R0=2; 1:R1=0; ok=1; x=2;