Test SB+dmbnaa+poar

ARM SB+dmbnaa+poar
"DMBdWRNaA FreAA PodWRAR FreRNa"
Cycle=FreAA PodWRAR FreRNa DMBdWRNaA
Prefetch=0:x=F,0:y=T,1:y=F,1:x=T
Com=Fr Fr
Orig=DMBdWRNaA FreAA PodWRAR FreRNa
{ ok=1;
%x0=x; %y0=y; %ok0=ok;
%y1=y; %x1=x; %ok1=ok;
}
 P0                 | P1                  ;
 MOV R0,#1          | MOV %T3,#1          ;
 STR R0,[%x0]       | LDREX R0,[%y1]      ;
 DMB                | STREX %T2,%T3,[%y1] ;
 LDREX R1,[%y0]     | CMP %T2,#0          ;
 STREX %T2,R1,[%y0] | BNE Fail1           ;
 CMP %T2,#0         | LDREX R1,[%x1]      ;
 BNE Fail0          | B Exit1             ;
 B Exit0            | Fail1:              ;
 Fail0:             | MOV R2,#0           ;
 MOV R2,#0          | STR R2,[%ok1]       ;
 STR R2,[%ok0]      | Exit1:              ;
 Exit0:             |                     ;
Observed
    0:R1=0; 1:R0=0; 1:R1=0; ok=1; y=1;