Test MP+dmbana+ctrlra

ARM MP+dmbana+ctrlra
"DMBdWWANa RfeNaR DpCtrldRRA FreAA"
Cycle=RfeNaR DpCtrldRRA FreAA DMBdWWANa
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMBdWWANa RfeNaR DpCtrldRRA FreAA
{ ok=1;
%x0=x; %y0=y; %ok0=ok;
%y1=y; %x1=x; %ok1=ok;
}
 P0                  | P1                 ;
 MOV %T3,#1          | LDREX R0,[%y1]     ;
 LDREX R0,[%x0]      | CMP R0,R0          ;
 STREX %T2,%T3,[%x0] | BNE LC00           ;
 CMP %T2,#0          | LC00:              ;
 BNE Fail0           | LDREX R1,[%x1]     ;
 DMB                 | STREX %T2,R1,[%x1] ;
 MOV R1,#1           | CMP %T2,#0         ;
 STR R1,[%y0]        | BNE Fail1          ;
 B Exit0             | B Exit1            ;
 Fail0:              | Fail1:             ;
 MOV R2,#0           | MOV R2,#0          ;
 STR R2,[%ok0]       | STR R2,[%ok1]      ;
 Exit0:              | Exit1:             ;
Observed
    0:R0=0; 1:R0=1; 1:R1=0; ok=0; x=1;