Test MP+dmb+pora

ARM MP+dmb+pora
"DMBdWW RfeNaR PodRRRA FreANa"
Cycle=RfeNaR PodRRRA FreANa DMBdWW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMBdWW RfeNaR PodRRRA FreANa
{ ok=1;
%x0=x; %y0=y;
%y1=y; %x1=x; %ok1=ok;
}
 P0           | P1                 ;
 MOV R0,#1    | LDREX R0,[%y1]     ;
 STR R0,[%x0] | LDREX R1,[%x1]     ;
 DMB          | STREX %T2,R1,[%x1] ;
 MOV R1,#1    | CMP %T2,#0         ;
 STR R1,[%y0] | BNE Fail1          ;
              | B Exit1            ;
              | Fail1:             ;
              | MOV R2,#0          ;
              | STR R2,[%ok1]      ;
              | Exit1:             ;
Observed
    1:R0=1; 1:R1=0; ok=0; x=1;
and 1:R0=1; 1:R1=0; ok=1; x=1;