Test MP+dmb+ctrlrr

ARM MP+dmb+ctrlrr
"DMBdWW RfeNaR DpCtrldRRR FreRNa"
Cycle=RfeNaR DpCtrldRRR FreRNa DMBdWW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMBdWW RfeNaR DpCtrldRRR FreRNa
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0           | P1             ;
 MOV R0,#1    | LDREX R0,[%y1] ;
 STR R0,[%x0] | CMP R0,R0      ;
 DMB          | BNE LC00       ;
 MOV R1,#1    | LC00:          ;
 STR R1,[%y0] | LDREX R1,[%x1] ;
Observed
    1:R0=1; 1:R1=0;