ARM MP+dmb+ctrlar "DMBdWW RfeNaA DpCtrldRAR FreRNa" Cycle=RfeNaA DpCtrldRAR FreRNa DMBdWW Prefetch=0:x=F,0:y=W,1:y=F,1:x=T Com=Rf Fr Orig=DMBdWW RfeNaA DpCtrldRAR FreRNa { ok=1; %x0=x; %y0=y; %y1=y; %x1=x; %ok1=ok; } P0 | P1 ; MOV R0,#1 | LDREX R0,[%y1] ; STR R0,[%x0] | STREX %T2,R0,[%y1] ; DMB | CMP %T2,#0 ; MOV R1,#1 | BNE Fail1 ; STR R1,[%y0] | CMP R0,R0 ; | BNE LC00 ; | LC00: ; | LDREX R1,[%x1] ; | B Exit1 ; | Fail1: ; | MOV R2,#0 ; | STR R2,[%ok1] ; | Exit1: ; Observed 1:R0=1; 1:R1=0; ok=1; y=1;