Test LB+ctrl+pora

ARM LB+ctrl+pora
"DpCtrldW RfeNaR PodRWRA RfeANa"
Cycle=RfeNaR PodRWRA RfeANa DpCtrldW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=DpCtrldW RfeNaR PodRWRA RfeANa
{ ok=1;
%x0=x; %y0=y;
%y1=y; %x1=x; %ok1=ok;
}
 P0           | P1                  ;
 LDR R0,[%x0] | LDREX R0,[%y1]      ;
 CMP R0,R0    | MOV %T3,#1          ;
 BNE LC00     | LDREX R1,[%x1]      ;
 LC00:        | STREX %T2,%T3,[%x1] ;
 MOV R1,#1    | CMP %T2,#0          ;
 STR R1,[%y0] | BNE Fail1           ;
              | B Exit1             ;
              | Fail1:              ;
              | MOV R2,#0           ;
              | STR R2,[%ok1]       ;
              | Exit1:              ;
Observed
    0:R0=1; 1:R0=1; 1:R1=0; ok=1; x=1;