Test LB+addrra+pora

ARM LB+addrra+pora
"DpAddrdWRA RfeAR PodRWRA RfeAR"
Cycle=RfeAR PodRWRA RfeAR DpAddrdWRA
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=DpAddrdWRA RfeAR PodRWRA RfeAR
{ ok=1;
%x0=x; %y0=y; %ok0=ok;
%y1=y; %x1=x; %ok1=ok;
}
 P0                  | P1                  ;
 LDREX R0,[%x0]      | LDREX R0,[%y1]      ;
 EOR R1,R0,R0        | MOV %T3,#1          ;
 ADD %T1,R1,%y0      | LDREX R1,[%x1]      ;
 MOV %T3,#1          | STREX %T2,%T3,[%x1] ;
 LDREX R2,[%T1]      | CMP %T2,#0          ;
 STREX %T2,%T3,[%T1] | BNE Fail1           ;
 CMP %T2,#0          | B Exit1             ;
 BNE Fail0           | Fail1:              ;
 B Exit0             | MOV R2,#0           ;
 Fail0:              | STR R2,[%ok1]       ;
 MOV R3,#0           | Exit1:              ;
 STR R3,[%ok0]       |                     ;
 Exit0:              |                     ;
Observed
    0:R0=1; 0:R2=0; 1:R0=1; 1:R1=0; ok=1; x=1; y=1;