Test LB+addrana+pora

ARM LB+addrana+pora
"DpAddrdWANa RfeNaR PodRWRA RfeAA"
Cycle=RfeNaR PodRWRA RfeAA DpAddrdWANa
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=DpAddrdWANa RfeNaR PodRWRA RfeAA
{ ok=1;
%x0=x; %y0=y; %ok0=ok;
%y1=y; %x1=x; %ok1=ok;
}
 P0                 | P1                  ;
 LDREX R0,[%x0]     | LDREX R0,[%y1]      ;
 STREX %T2,R0,[%x0] | MOV %T3,#1          ;
 CMP %T2,#0         | LDREX R1,[%x1]      ;
 BNE Fail0          | STREX %T2,%T3,[%x1] ;
 EOR R1,R0,R0       | CMP %T2,#0          ;
 MOV R2,#1          | BNE Fail1           ;
 STR R2,[R1,%y0]    | B Exit1             ;
 B Exit0            | Fail1:              ;
 Fail0:             | MOV R2,#0           ;
 MOV R3,#0          | STR R2,[%ok1]       ;
 STR R3,[%ok0]      | Exit1:              ;
 Exit0:             |                     ;
Observed
    0:R0=1; 1:R0=1; 1:R1=0; ok=1; x=1;