Test Z6.3+rfinar-datarna+dmb+addr

Executions for behaviour: "0:R1=0 ; 2:R0=0 ; 2:R2=0 ; y=1"

Executions for behaviour: "0:R1=0 ; 2:R0=1 ; 2:R2=0 ; y=1"

Executions for behaviour: "0:R1=0 ; 2:R0=0 ; 2:R2=1 ; y=1"

Executions for behaviour: "0:R1=0 ; 2:R0=1 ; 2:R2=1 ; y=1"

Executions for behaviour: "0:R1=0 ; 2:R0=0 ; 2:R2=0 ; y=2"

Executions for behaviour: "0:R1=0 ; 2:R0=1 ; 2:R2=0 ; y=2"

Executions for behaviour: "0:R1=0 ; 2:R0=0 ; 2:R2=1 ; y=2"

Executions for behaviour: "0:R1=0 ; 2:R0=1 ; 2:R2=1 ; y=2"

ARM Z6.3+rfinar-datarna+dmb+addr
"RfiNaR DpDatadWRNa Wse DMBdWW Rfe DpAddrdR Fre"
Cycle=RfiNaR DpDatadWRNa Wse DMBdWW Rfe DpAddrdR Fre
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Ws Rf Fr
Orig=RfiNaR DpDatadWRNa Wse DMBdWW Rfe DpAddrdR Fre
{
%x0=x; %y0=y;
%y1=y; %z1=z;
%z2=z; %x2=x;
}
 P0             | P1           | P2              ;
 MOV R0,#1      | MOV R0,#2    | LDR R0,[%z2]    ;
 STR R0,[%x0]   | STR R0,[%y1] | EOR R1,R0,R0    ;
 LDREX R1,[%x0] | DMB          | LDR R2,[R1,%x2] ;
 EOR R2,R1,R1   | MOV R1,#1    |                 ;
 ADD R2,R2,#1   | STR R1,[%z1] |                 ;
 STR R2,[%y0]   |              |                 ;
Observed
    0:R1=0; 2:R0=0; 2:R2=0; y=1;
and 0:R1=0; 2:R0=1; 2:R2=0; y=1;
and 0:R1=0; 2:R0=0; 2:R2=1; y=1;
and 0:R1=0; 2:R0=1; 2:R2=1; y=1;
and 0:R1=0; 2:R0=0; 2:R2=0; y=2;
and 0:R1=0; 2:R0=1; 2:R2=0; y=2;
and 0:R1=0; 2:R0=0; 2:R2=1; y=2;
and 0:R1=0; 2:R0=1; 2:R2=1; y=2;