Test Z6.3+dmb+rfinar-datarna+addr

Executions for behaviour: "1:R1=0 ; 2:R0=0 ; 2:R2=0 ; y=1"

Executions for behaviour: "1:R1=0 ; 2:R0=1 ; 2:R2=0 ; y=1"

Executions for behaviour: "1:R1=0 ; 2:R0=0 ; 2:R2=1 ; y=1"

Executions for behaviour: "1:R1=0 ; 2:R0=1 ; 2:R2=1 ; y=1"

Executions for behaviour: "1:R1=0 ; 2:R0=0 ; 2:R2=0 ; y=2"

Executions for behaviour: "1:R1=1 ; 2:R0=0 ; 2:R2=0 ; y=2"

Executions for behaviour: "1:R1=0 ; 2:R0=1 ; 2:R2=0 ; y=2"

Executions for behaviour: "1:R1=0 ; 2:R0=0 ; 2:R2=1 ; y=2"

Executions for behaviour: "1:R1=1 ; 2:R0=0 ; 2:R2=1 ; y=2"

Executions for behaviour: "1:R1=0 ; 2:R0=1 ; 2:R2=1 ; y=2"

Executions for behaviour: "1:R1=1 ; 2:R0=1 ; 2:R2=1 ; y=2"

ARM Z6.3+dmb+rfinar-datarna+addr
"DMBdWW Wse RfiNaR DpDatadWRNa Rfe DpAddrdR Fre"
Cycle=RfiNaR DpDatadWRNa Rfe DpAddrdR Fre DMBdWW Wse
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Ws Rf Fr
Orig=DMBdWW Wse RfiNaR DpDatadWRNa Rfe DpAddrdR Fre
{
%x0=x; %y0=y;
%y1=y; %z1=z;
%z2=z; %x2=x;
}
 P0           | P1             | P2              ;
 MOV R0,#1    | MOV R0,#2      | LDR R0,[%z2]    ;
 STR R0,[%x0] | STR R0,[%y1]   | EOR R1,R0,R0    ;
 DMB          | LDREX R1,[%y1] | LDR R2,[R1,%x2] ;
 MOV R1,#1    | EOR R2,R1,R1   |                 ;
 STR R1,[%y0] | ADD R2,R2,#1   |                 ;
              | STR R2,[%z1]   |                 ;
Observed
    1:R1=0; 2:R0=0; 2:R2=0; y=1;
and 1:R1=0; 2:R0=1; 2:R2=0; y=1;
and 1:R1=0; 2:R0=0; 2:R2=1; y=1;
and 1:R1=0; 2:R0=1; 2:R2=1; y=1;
and 1:R1=0; 2:R0=0; 2:R2=0; y=2;
and 1:R1=1; 2:R0=0; 2:R2=0; y=2;
and 1:R1=0; 2:R0=1; 2:R2=0; y=2;
and 1:R1=0; 2:R0=0; 2:R2=1; y=2;
and 1:R1=1; 2:R0=0; 2:R2=1; y=2;
and 1:R1=0; 2:R0=1; 2:R2=1; y=2;
and 1:R1=1; 2:R0=1; 2:R2=1; y=2;