Test Z6.2+rfinar-datarna+data+addr

Executions for behaviour: "0:R1=0 ; 1:R0=0 ; 2:R0=0 ; x=1"

Executions for behaviour: "0:R1=0 ; 1:R0=1 ; 2:R0=0 ; x=1"

Executions for behaviour: "0:R1=0 ; 1:R0=0 ; 2:R0=1 ; x=1"

Executions for behaviour: "0:R1=0 ; 1:R0=1 ; 2:R0=1 ; x=1"

Executions for behaviour: "0:R1=0 ; 1:R0=0 ; 2:R0=0 ; x=2"

Executions for behaviour: "0:R1=1 ; 1:R0=0 ; 2:R0=0 ; x=2"

Executions for behaviour: "0:R1=0 ; 1:R0=1 ; 2:R0=0 ; x=2"

Executions for behaviour: "0:R1=1 ; 1:R0=1 ; 2:R0=0 ; x=2"

Executions for behaviour: "0:R1=0 ; 1:R0=0 ; 2:R0=1 ; x=2"

Executions for behaviour: "0:R1=1 ; 1:R0=0 ; 2:R0=1 ; x=2"

Executions for behaviour: "0:R1=0 ; 1:R0=1 ; 2:R0=1 ; x=2"

ARM Z6.2+rfinar-datarna+data+addr
"RfiNaR DpDatadWRNa Rfe DpDatadW Rfe DpAddrdW Wse"
Cycle=RfiNaR DpDatadWRNa Rfe DpDatadW Rfe DpAddrdW Wse
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=W
Com=Rf Rf Ws
Orig=RfiNaR DpDatadWRNa Rfe DpDatadW Rfe DpAddrdW Wse
{
%x0=x; %y0=y;
%y1=y; %z1=z;
%z2=z; %x2=x;
}
 P0             | P1           | P2              ;
 MOV R0,#2      | LDR R0,[%y1] | LDR R0,[%z2]    ;
 STR R0,[%x0]   | EOR R1,R0,R0 | EOR R1,R0,R0    ;
 LDREX R1,[%x0] | ADD R1,R1,#1 | MOV R2,#1       ;
 EOR R2,R1,R1   | STR R1,[%z1] | STR R2,[R1,%x2] ;
 ADD R2,R2,#1   |              |                 ;
 STR R2,[%y0]   |              |                 ;
Observed
    0:R1=0; 1:R0=0; 2:R0=0; x=1;
and 0:R1=0; 1:R0=1; 2:R0=0; x=1;
and 0:R1=0; 1:R0=0; 2:R0=1; x=1;
and 0:R1=0; 1:R0=1; 2:R0=1; x=1;
and 0:R1=0; 1:R0=0; 2:R0=0; x=2;
and 0:R1=1; 1:R0=0; 2:R0=0; x=2;
and 0:R1=0; 1:R0=1; 2:R0=0; x=2;
and 0:R1=1; 1:R0=1; 2:R0=0; x=2;
and 0:R1=0; 1:R0=0; 2:R0=1; x=2;
and 0:R1=1; 1:R0=0; 2:R0=1; x=2;
and 0:R1=0; 1:R0=1; 2:R0=1; x=2;