Test Z6.0+rfinar-datarna+addr+dmb

Executions for behaviour: "0:R1=0 ; 1:R0=0 ; 2:R1=0 ; z=1"

Executions for behaviour: "0:R1=0 ; 1:R0=1 ; 2:R1=0 ; z=1"

Executions for behaviour: "0:R1=0 ; 1:R0=0 ; 2:R1=1 ; z=1"

Executions for behaviour: "0:R1=0 ; 1:R0=1 ; 2:R1=1 ; z=1"

Executions for behaviour: "0:R1=0 ; 1:R0=0 ; 2:R1=0 ; z=2"

Executions for behaviour: "0:R1=0 ; 1:R0=1 ; 2:R1=0 ; z=2"

Executions for behaviour: "0:R1=0 ; 1:R0=0 ; 2:R1=1 ; z=2"

Executions for behaviour: "0:R1=0 ; 1:R0=1 ; 2:R1=1 ; z=2"

ARM Z6.0+rfinar-datarna+addr+dmb
"RfiNaR DpDatadWRNa Rfe DpAddrdW Wse DMBdWR Fre"
Cycle=RfiNaR DpDatadWRNa Rfe DpAddrdW Wse DMBdWR Fre
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Rf Ws Fr
Orig=RfiNaR DpDatadWRNa Rfe DpAddrdW Wse DMBdWR Fre
{
%x0=x; %y0=y;
%y1=y; %z1=z;
%z2=z; %x2=x;
}
 P0             | P1              | P2           ;
 MOV R0,#1      | LDR R0,[%y1]    | MOV R0,#2    ;
 STR R0,[%x0]   | EOR R1,R0,R0    | STR R0,[%z2] ;
 LDREX R1,[%x0] | MOV R2,#1       | DMB          ;
 EOR R2,R1,R1   | STR R2,[R1,%z1] | LDR R1,[%x2] ;
 ADD R2,R2,#1   |                 |              ;
 STR R2,[%y0]   |                 |              ;
Observed
    0:R1=0; 1:R0=0; 2:R1=0; z=1;
and 0:R1=0; 1:R0=1; 2:R1=0; z=1;
and 0:R1=0; 1:R0=0; 2:R1=1; z=1;
and 0:R1=0; 1:R0=1; 2:R1=1; z=1;
and 0:R1=0; 1:R0=0; 2:R1=0; z=2;
and 0:R1=0; 1:R0=1; 2:R1=0; z=2;
and 0:R1=0; 1:R0=0; 2:R1=1; z=2;
and 0:R1=0; 1:R0=1; 2:R1=1; z=2;