Test Z6.0+dmb+addr+rfinar-addrrna

Executions for behaviour: "1:R0=0 ; 2:R1=0 ; 2:R3=0 ; z=1"

Executions for behaviour: "1:R0=1 ; 2:R1=0 ; 2:R3=0 ; z=1"

Executions for behaviour: "1:R0=0 ; 2:R1=0 ; 2:R3=1 ; z=1"

Executions for behaviour: "1:R0=1 ; 2:R1=0 ; 2:R3=1 ; z=1"

Executions for behaviour: "1:R0=0 ; 2:R1=0 ; 2:R3=0 ; z=2"

Executions for behaviour: "1:R0=1 ; 2:R1=0 ; 2:R3=0 ; z=2"

Executions for behaviour: "1:R0=0 ; 2:R1=1 ; 2:R3=0 ; z=2"

Executions for behaviour: "1:R0=0 ; 2:R1=0 ; 2:R3=1 ; z=2"

Executions for behaviour: "1:R0=1 ; 2:R1=0 ; 2:R3=1 ; z=2"

Executions for behaviour: "1:R0=0 ; 2:R1=1 ; 2:R3=1 ; z=2"

Executions for behaviour: "1:R0=1 ; 2:R1=1 ; 2:R3=1 ; z=2"

ARM Z6.0+dmb+addr+rfinar-addrrna
"DMBdWW Rfe DpAddrdW Wse RfiNaR DpAddrdRRNa Fre"
Cycle=RfiNaR DpAddrdRRNa Fre DMBdWW Rfe DpAddrdW Wse
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Rf Ws Fr
Orig=DMBdWW Rfe DpAddrdW Wse RfiNaR DpAddrdRRNa Fre
{
%x0=x; %y0=y;
%y1=y; %z1=z;
%z2=z; %x2=x;
}
 P0           | P1              | P2              ;
 MOV R0,#1    | LDR R0,[%y1]    | MOV R0,#2       ;
 STR R0,[%x0] | EOR R1,R0,R0    | STR R0,[%z2]    ;
 DMB          | MOV R2,#1       | LDREX R1,[%z2]  ;
 MOV R1,#1    | STR R2,[R1,%z1] | EOR R2,R1,R1    ;
 STR R1,[%y0] |                 | LDR R3,[R2,%x2] ;
Observed
    1:R0=0; 2:R1=0; 2:R3=0; z=1;
and 1:R0=1; 2:R1=0; 2:R3=0; z=1;
and 1:R0=0; 2:R1=0; 2:R3=1; z=1;
and 1:R0=1; 2:R1=0; 2:R3=1; z=1;
and 1:R0=0; 2:R1=0; 2:R3=0; z=2;
and 1:R0=1; 2:R1=0; 2:R3=0; z=2;
and 1:R0=0; 2:R1=1; 2:R3=0; z=2;
and 1:R0=0; 2:R1=0; 2:R3=1; z=2;
and 1:R0=1; 2:R1=0; 2:R3=1; z=2;
and 1:R0=0; 2:R1=1; 2:R3=1; z=2;
and 1:R0=1; 2:R1=1; 2:R3=1; z=2;