Test WRW+WR+data+rfinar-addrrna

Executions for behaviour: "1:R0=0 ; 2:R1=0 ; 2:R3=0 ; y=1"

Executions for behaviour: "1:R0=1 ; 2:R1=0 ; 2:R3=0 ; y=1"

Executions for behaviour: "1:R0=0 ; 2:R1=0 ; 2:R3=1 ; y=1"

Executions for behaviour: "1:R0=1 ; 2:R1=0 ; 2:R3=1 ; y=1"

Executions for behaviour: "1:R0=0 ; 2:R1=0 ; 2:R3=0 ; y=2"

Executions for behaviour: "1:R0=1 ; 2:R1=0 ; 2:R3=0 ; y=2"

Executions for behaviour: "1:R0=0 ; 2:R1=1 ; 2:R3=0 ; y=2"

Executions for behaviour: "1:R0=1 ; 2:R1=1 ; 2:R3=0 ; y=2"

Executions for behaviour: "1:R0=0 ; 2:R1=0 ; 2:R3=1 ; y=2"

Executions for behaviour: "1:R0=1 ; 2:R1=0 ; 2:R3=1 ; y=2"

Executions for behaviour: "1:R0=0 ; 2:R1=1 ; 2:R3=1 ; y=2"

Executions for behaviour: "1:R0=1 ; 2:R1=1 ; 2:R3=1 ; y=2"

ARM WRW+WR+data+rfinar-addrrna
"Rfe DpDatadW Wse RfiNaR DpAddrdRRNa Fre"
Cycle=RfiNaR DpAddrdRRNa Fre Rfe DpDatadW Wse
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Ws Fr
Orig=Rfe DpDatadW Wse RfiNaR DpAddrdRRNa Fre
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0           | P1           | P2              ;
 MOV R0,#1    | LDR R0,[%x1] | MOV R0,#2       ;
 STR R0,[%x0] | EOR R1,R0,R0 | STR R0,[%y2]    ;
              | ADD R1,R1,#1 | LDREX R1,[%y2]  ;
              | STR R1,[%y1] | EOR R2,R1,R1    ;
              |              | LDR R3,[R2,%x2] ;
Observed
    1:R0=0; 2:R1=0; 2:R3=0; y=1;
and 1:R0=1; 2:R1=0; 2:R3=0; y=1;
and 1:R0=0; 2:R1=0; 2:R3=1; y=1;
and 1:R0=1; 2:R1=0; 2:R3=1; y=1;
and 1:R0=0; 2:R1=0; 2:R3=0; y=2;
and 1:R0=1; 2:R1=0; 2:R3=0; y=2;
and 1:R0=0; 2:R1=1; 2:R3=0; y=2;
and 1:R0=1; 2:R1=1; 2:R3=0; y=2;
and 1:R0=0; 2:R1=0; 2:R3=1; y=2;
and 1:R0=1; 2:R1=0; 2:R3=1; y=2;
and 1:R0=0; 2:R1=1; 2:R3=1; y=2;
and 1:R0=1; 2:R1=1; 2:R3=1; y=2;