Test WRC+dmb+addr-fri-rfinar-addrrna

Executions for behaviour: "1:R0=0 ; 2:R0=0 ; 2:R2=0 ; 2:R4=0 ; 2:R6=0"

Executions for behaviour: "1:R0=1 ; 2:R0=0 ; 2:R2=0 ; 2:R4=0 ; 2:R6=0"

Executions for behaviour: "1:R0=0 ; 2:R0=1 ; 2:R2=0 ; 2:R4=0 ; 2:R6=0"

Executions for behaviour: "1:R0=0 ; 2:R0=0 ; 2:R2=0 ; 2:R4=0 ; 2:R6=1"

Executions for behaviour: "1:R0=1 ; 2:R0=0 ; 2:R2=0 ; 2:R4=0 ; 2:R6=1"

Executions for behaviour: "1:R0=0 ; 2:R0=1 ; 2:R2=0 ; 2:R4=0 ; 2:R6=1"

Executions for behaviour: "1:R0=1 ; 2:R0=1 ; 2:R2=0 ; 2:R4=0 ; 2:R6=1"

ARM WRC+dmb+addr-fri-rfinar-addrrna
"Rfe DMBdRW Rfe DpAddrdR Fri RfiNaR DpAddrdRRNa Fre"
Cycle=RfiNaR DpAddrdRRNa Fre Rfe DMBdRW Rfe DpAddrdR Fri
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=Rfe DMBdRW Rfe DpAddrdR Fri RfiNaR DpAddrdRRNa Fre
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %z2=z; %x2=x;
}
 P0           | P1           | P2              ;
 MOV R0,#1    | LDR R0,[%x1] | LDR R0,[%y2]    ;
 STR R0,[%x0] | DMB          | EOR R1,R0,R0    ;
              | MOV R1,#1    | LDR R2,[R1,%z2] ;
              | STR R1,[%y1] | MOV R3,#1       ;
              |              | STR R3,[%z2]    ;
              |              | LDREX R4,[%z2]  ;
              |              | EOR R5,R4,R4    ;
              |              | LDR R6,[R5,%x2] ;
Observed
    1:R0=0; 2:R0=0; 2:R2=0; 2:R4=0; 2:R6=0;
and 1:R0=1; 2:R0=0; 2:R2=0; 2:R4=0; 2:R6=0;
and 1:R0=0; 2:R0=1; 2:R2=0; 2:R4=0; 2:R6=0;
and 1:R0=0; 2:R0=0; 2:R2=0; 2:R4=0; 2:R6=1;
and 1:R0=1; 2:R0=0; 2:R2=0; 2:R4=0; 2:R6=1;
and 1:R0=0; 2:R0=1; 2:R2=0; 2:R4=0; 2:R6=1;
and 1:R0=1; 2:R0=1; 2:R2=0; 2:R4=0; 2:R6=1;