Test R+rfi-data+rfinar-addrrna

Executions for behaviour: "0:R1=1 ; 1:R1=0 ; 1:R3=0 ; y=1"

Executions for behaviour: "0:R1=1 ; 1:R1=0 ; 1:R3=1 ; y=1"

Executions for behaviour: "0:R1=1 ; 1:R1=0 ; 1:R3=0 ; y=2"

Executions for behaviour: "0:R1=1 ; 1:R1=1 ; 1:R3=0 ; y=2"

Executions for behaviour: "0:R1=1 ; 1:R1=0 ; 1:R3=1 ; y=2"

Executions for behaviour: "0:R1=1 ; 1:R1=1 ; 1:R3=1 ; y=2"

ARM R+rfi-data+rfinar-addrrna
"Rfi DpDatadW Wse RfiNaR DpAddrdRRNa Fre"
Cycle=Rfi DpDatadW Wse RfiNaR DpAddrdRRNa Fre
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Ws Fr
Orig=Rfi DpDatadW Wse RfiNaR DpAddrdRRNa Fre
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0           | P1              ;
 MOV R0,#1    | MOV R0,#2       ;
 STR R0,[%x0] | STR R0,[%y1]    ;
 LDR R1,[%x0] | LDREX R1,[%y1]  ;
 EOR R2,R1,R1 | EOR R2,R1,R1    ;
 ADD R2,R2,#1 | LDR R3,[R2,%x1] ;
 STR R2,[%y0] |                 ;
Observed
    0:R1=1; 1:R1=0; 1:R3=0; y=1;
and 0:R1=1; 1:R1=0; 1:R3=1; y=1;
and 0:R1=1; 1:R1=0; 1:R3=0; y=2;
and 0:R1=1; 1:R1=1; 1:R3=0; y=2;
and 0:R1=1; 1:R1=0; 1:R3=1; y=2;
and 0:R1=1; 1:R1=1; 1:R3=1; y=2;