Test ISA2+rfinar-datarna+data+dmb

Executions for behaviour: "0:R1=0 ; 1:R0=0 ; 2:R0=0 ; 2:R1=0"

Executions for behaviour: "0:R1=0 ; 1:R0=1 ; 2:R0=0 ; 2:R1=0"

Executions for behaviour: "0:R1=0 ; 1:R0=0 ; 2:R0=1 ; 2:R1=0"

Executions for behaviour: "0:R1=0 ; 1:R0=1 ; 2:R0=1 ; 2:R1=0"

Executions for behaviour: "0:R1=0 ; 1:R0=0 ; 2:R0=0 ; 2:R1=1"

Executions for behaviour: "0:R1=0 ; 1:R0=1 ; 2:R0=0 ; 2:R1=1"

Executions for behaviour: "0:R1=0 ; 1:R0=0 ; 2:R0=1 ; 2:R1=1"

Executions for behaviour: "0:R1=0 ; 1:R0=1 ; 2:R0=1 ; 2:R1=1"

ARM ISA2+rfinar-datarna+data+dmb
"RfiNaR DpDatadWRNa Rfe DpDatadW Rfe DMBdRR Fre"
Cycle=RfiNaR DpDatadWRNa Rfe DpDatadW Rfe DMBdRR Fre
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Rf Rf Fr
Orig=RfiNaR DpDatadWRNa Rfe DpDatadW Rfe DMBdRR Fre
{
%x0=x; %y0=y;
%y1=y; %z1=z;
%z2=z; %x2=x;
}
 P0             | P1           | P2           ;
 MOV R0,#1      | LDR R0,[%y1] | LDR R0,[%z2] ;
 STR R0,[%x0]   | EOR R1,R0,R0 | DMB          ;
 LDREX R1,[%x0] | ADD R1,R1,#1 | LDR R1,[%x2] ;
 EOR R2,R1,R1   | STR R1,[%z1] |              ;
 ADD R2,R2,#1   |              |              ;
 STR R2,[%y0]   |              |              ;
Observed
    0:R1=0; 1:R0=0; 2:R0=0; 2:R1=0;
and 0:R1=0; 1:R0=1; 2:R0=0; 2:R1=0;
and 0:R1=0; 1:R0=0; 2:R0=1; 2:R1=0;
and 0:R1=0; 1:R0=1; 2:R0=1; 2:R1=0;
and 0:R1=0; 1:R0=0; 2:R0=0; 2:R1=1;
and 0:R1=0; 1:R0=1; 2:R0=0; 2:R1=1;
and 0:R1=0; 1:R0=0; 2:R0=1; 2:R1=1;
and 0:R1=0; 1:R0=1; 2:R0=1; 2:R1=1;