Executions for behaviour:
"0:R0=0 ; 0:R1=1 ; 1:R0=1 ; 1:R1=2 ; 2:R0=1 ; ok=1 ; x=1 ; y=2"
ARM Z6.1+rfiana-data+rfiar-datarna+data
"RfiANa DpDatadW WseNaA RfiAR DpDatadWRNa Rfe DpDatadW WseNaA"
Cycle=RfiANa DpDatadW WseNaA RfiAR DpDatadWRNa Rfe DpDatadW WseNaA
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=W
Com=Ws Rf Ws
Orig=RfiANa DpDatadW WseNaA RfiAR DpDatadWRNa Rfe DpDatadW WseNaA
{ ok=1;
%x0=x; %y0=y; %ok0=ok;
%y1=y; %z1=z; %ok1=ok;
%z2=z; %x2=x;
}
P0 | P1 | P2 ;
MOV %T3,#2 | MOV %T3,#2 | LDR R0,[%z2] ;
LDREX R0,[%x0] | LDREX R0,[%y1] | EOR R1,R0,R0 ;
STREX %T2,%T3,[%x0] | STREX %T2,%T3,[%y1] | ADD R1,R1,#1 ;
CMP %T2,#0 | CMP %T2,#0 | STR R1,[%x2] ;
BNE Fail0 | BNE Fail1 | ;
LDR R1,[%x0] | LDREX R1,[%y1] | ;
EOR R2,R1,R1 | EOR R2,R1,R1 | ;
ADD R2,R2,#1 | ADD R2,R2,#1 | ;
STR R2,[%y0] | STR R2,[%z1] | ;
B Exit0 | B Exit1 | ;
Fail0: | Fail1: | ;
MOV R3,#0 | MOV R3,#0 | ;
STR R3,[%ok0] | STR R3,[%ok1] | ;
Exit0: | Exit1: | ;
Observed
0:R0=0; 0:R1=1; 1:R0=1; 1:R1=2; 2:R0=1; ok=1; x=1; y=2;