Test Z6.0+dmb+dmb+rfiar-addrrna

Executions for behaviour: "1:R0=1 ; 2:R0=1 ; 2:R1=2 ; 2:R3=0 ; ok=1 ; z=2"

ARM Z6.0+dmb+dmb+rfiar-addrrna
"DMBdWW Rfe DMBdRW WseNaA RfiAR DpAddrdRRNa Fre"
Cycle=RfiAR DpAddrdRRNa Fre DMBdWW Rfe DMBdRW WseNaA
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Rf Ws Fr
Orig=DMBdWW Rfe DMBdRW WseNaA RfiAR DpAddrdRRNa Fre
{ ok=1;
%x0=x; %y0=y;
%y1=y; %z1=z;
%z2=z; %x2=x; %ok2=ok;
}
 P0           | P1           | P2                  ;
 MOV R0,#1    | LDR R0,[%y1] | MOV %T3,#2          ;
 STR R0,[%x0] | DMB          | LDREX R0,[%z2]      ;
 DMB          | MOV R1,#1    | STREX %T2,%T3,[%z2] ;
 MOV R1,#1    | STR R1,[%z1] | CMP %T2,#0          ;
 STR R1,[%y0] |              | BNE Fail2           ;
              |              | LDREX R1,[%z2]      ;
              |              | EOR R2,R1,R1        ;
              |              | LDR R3,[R2,%x2]     ;
              |              | B Exit2             ;
              |              | Fail2:              ;
              |              | MOV R4,#0           ;
              |              | STR R4,[%ok2]       ;
              |              | Exit2:              ;
Observed
    1:R0=1; 2:R0=1; 2:R1=2; 2:R3=0; ok=1; z=2;