Test WWC+poaa+addrana+A

Executions for behaviour: "0:R0=1 ; 1:R0=2 ; 1:R1=0 ; 2:R0=1 ; ok=1 ; x=2 ; y=1"

ARM WWC+poaa+addrana+A
"RfeAA PodRWAA RfeAA DpAddrdWANa WseNaA"
Cycle=RfeAA PodRWAA RfeAA DpAddrdWANa WseNaA
Prefetch=1:x=F,1:y=W,2:y=F,2:x=W
Com=Rf Rf Ws
Orig=RfeAA PodRWAA RfeAA DpAddrdWANa WseNaA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0                  | P1                  | P2                 ;
 MOV %T3,#2          | LDREX R0,[%x1]      | LDREX R0,[%y2]     ;
 LDREX R0,[%x0]      | STREX %T2,R0,[%x1]  | STREX %T2,R0,[%y2] ;
 STREX %T2,%T3,[%x0] | CMP %T2,#0          | CMP %T2,#0         ;
 CMP %T2,#0          | BNE Fail1           | BNE Fail2          ;
 BNE Fail0           | MOV %T3,#1          | EOR R1,R0,R0       ;
 B Exit0             | LDREX R1,[%y1]      | MOV R2,#1          ;
 Fail0:              | STREX %T2,%T3,[%y1] | STR R2,[R1,%x2]    ;
 MOV R1,#0           | CMP %T2,#0          | B Exit2            ;
 STR R1,[%ok0]       | BNE Fail1           | Fail2:             ;
 Exit0:              | B Exit1             | MOV R3,#0          ;
                     | Fail1:              | STR R3,[%ok2]      ;
                     | MOV R2,#0           | Exit2:             ;
                     | STR R2,[%ok1]       |                    ;
                     | Exit1:              |                    ;
Observed
    0:R0=1; 1:R0=2; 1:R1=0; 2:R0=1; ok=1; x=2; y=1;