Test WRW+2W+addr+rfiar-datarna

Executions for behaviour: "1:R0=1 ; 2:R0=1 ; 2:R1=2 ; ok=1 ; x=1 ; y=2"

Executions for behaviour: "1:R0=1 ; 2:R0=1 ; 2:R1=2 ; ok=1 ; x=2 ; y=2"

ARM WRW+2W+addr+rfiar-datarna
"Rfe DpAddrdW WseNaA RfiAR DpDatadWRNa Wse"
Cycle=RfiAR DpDatadWRNa Wse Rfe DpAddrdW WseNaA
Prefetch=1:x=F,1:y=W,2:y=F,2:x=W
Com=Rf Ws Ws
Orig=Rfe DpAddrdW WseNaA RfiAR DpDatadWRNa Wse
{ ok=1;
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x; %ok2=ok;
}
 P0           | P1              | P2                  ;
 MOV R0,#2    | LDR R0,[%x1]    | MOV %T3,#2          ;
 STR R0,[%x0] | EOR R1,R0,R0    | LDREX R0,[%y2]      ;
              | MOV R2,#1       | STREX %T2,%T3,[%y2] ;
              | STR R2,[R1,%y1] | CMP %T2,#0          ;
              |                 | BNE Fail2           ;
              |                 | LDREX R1,[%y2]      ;
              |                 | EOR R2,R1,R1        ;
              |                 | ADD R2,R2,#1        ;
              |                 | STR R2,[%x2]        ;
              |                 | B Exit2             ;
              |                 | Fail2:              ;
              |                 | MOV R3,#0           ;
              |                 | STR R3,[%ok2]       ;
              |                 | Exit2:              ;
Observed
    1:R0=1; 2:R0=1; 2:R1=2; ok=1; x=1; y=2;
and 1:R0=1; 2:R0=1; 2:R1=2; ok=1; x=2; y=2;