Test WRC+pora+ctrlnaa+A

Executions for behaviour: "0:R0=0 ; 1:R0=1 ; 1:R1=0 ; 2:R0=1 ; 2:R1=0 ; ok=1 ; x=1 ; y=1"

ARM WRC+pora+ctrlnaa+A
"RfeAR PodRWRA RfeANa DpCtrldRNaA FreAA"
Cycle=RfeANa DpCtrldRNaA FreAA RfeAR PodRWRA
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=RfeAR PodRWRA RfeANa DpCtrldRNaA FreAA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0                  | P1                  | P2                 ;
 MOV %T3,#1          | LDREX R0,[%x1]      | LDR R0,[%y2]       ;
 LDREX R0,[%x0]      | MOV %T3,#1          | CMP R0,R0          ;
 STREX %T2,%T3,[%x0] | LDREX R1,[%y1]      | BNE LC00           ;
 CMP %T2,#0          | STREX %T2,%T3,[%y1] | LC00:              ;
 BNE Fail0           | CMP %T2,#0          | LDREX R1,[%x2]     ;
 B Exit0             | BNE Fail1           | STREX %T2,R1,[%x2] ;
 Fail0:              | B Exit1             | CMP %T2,#0         ;
 MOV R1,#0           | Fail1:              | BNE Fail2          ;
 STR R1,[%ok0]       | MOV R2,#0           | B Exit2            ;
 Exit0:              | STR R2,[%ok1]       | Fail2:             ;
                     | Exit1:              | MOV R2,#0          ;
                     |                     | STR R2,[%ok2]      ;
                     |                     | Exit2:             ;
Observed
    0:R0=0; 1:R0=1; 1:R1=0; 2:R0=1; 2:R1=0; ok=1; x=1; y=1;