Test WRC+dmbra+porr+A

Executions for behaviour: "0:R0=0 ; 1:R0=1 ; 1:R1=0 ; 2:R0=1 ; 2:R1=0 ; ok=1 ; x=1 ; y=1"

ARM WRC+dmbra+porr+A
"RfeAR DMBdRWRA RfeAR PodRRRR FreRA"
Cycle=RfeAR PodRRRR FreRA RfeAR DMBdRWRA
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=RfeAR DMBdRWRA RfeAR PodRRRR FreRA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x;
}
 P0                  | P1                  | P2             ;
 MOV %T3,#1          | LDREX R0,[%x1]      | LDREX R0,[%y2] ;
 LDREX R0,[%x0]      | DMB                 | LDREX R1,[%x2] ;
 STREX %T2,%T3,[%x0] | MOV %T3,#1          |                ;
 CMP %T2,#0          | LDREX R1,[%y1]      |                ;
 BNE Fail0           | STREX %T2,%T3,[%y1] |                ;
 B Exit0             | CMP %T2,#0          |                ;
 Fail0:              | BNE Fail1           |                ;
 MOV R1,#0           | B Exit1             |                ;
 STR R1,[%ok0]       | Fail1:              |                ;
 Exit0:              | MOV R2,#0           |                ;
                     | STR R2,[%ok1]       |                ;
                     | Exit1:              |                ;
Observed
    0:R0=0; 1:R0=1; 1:R1=0; 2:R0=1; 2:R1=0; ok=1; x=1; y=1;