Test WRC+dmbaa+pora

Executions for behaviour: "1:R0=1 ; 1:R1=0 ; 2:R0=1 ; 2:R1=0 ; ok=0 ; x=1 ; y=1"

Executions for behaviour: "1:R0=1 ; 1:R1=0 ; 2:R0=1 ; 2:R1=0 ; ok=1 ; x=1 ; y=1"

ARM WRC+dmbaa+pora
"RfeNaA DMBdRWAA RfeAR PodRRRA FreANa"
Cycle=RfeNaA DMBdRWAA RfeAR PodRRRA FreANa
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=RfeNaA DMBdRWAA RfeAR PodRRRA FreANa
{ ok=1;
%x0=x;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0           | P1                  | P2                 ;
 MOV R0,#1    | LDREX R0,[%x1]      | LDREX R0,[%y2]     ;
 STR R0,[%x0] | STREX %T2,R0,[%x1]  | LDREX R1,[%x2]     ;
              | CMP %T2,#0          | STREX %T2,R1,[%x2] ;
              | BNE Fail1           | CMP %T2,#0         ;
              | DMB                 | BNE Fail2          ;
              | MOV %T3,#1          | B Exit2            ;
              | LDREX R1,[%y1]      | Fail2:             ;
              | STREX %T2,%T3,[%y1] | MOV R2,#0          ;
              | CMP %T2,#0          | STR R2,[%ok2]      ;
              | BNE Fail1           | Exit2:             ;
              | B Exit1             |                    ;
              | Fail1:              |                    ;
              | MOV R2,#0           |                    ;
              | STR R2,[%ok1]       |                    ;
              | Exit1:              |                    ;
Observed
    1:R0=1; 1:R1=0; 2:R0=1; 2:R1=0; ok=0; x=1; y=1;
and 1:R0=1; 1:R1=0; 2:R0=1; 2:R1=0; ok=1; x=1; y=1;