Test WRC+dmb+ctrlar

Executions for behaviour: "1:R0=1 ; 2:R0=1 ; 2:R1=0 ; ok=1 ; y=1"

ARM WRC+dmb+ctrlar
"Rfe DMBdRW RfeNaA DpCtrldRAR FreRNa"
Cycle=Rfe DMBdRW RfeNaA DpCtrldRAR FreRNa
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=Rfe DMBdRW RfeNaA DpCtrldRAR FreRNa
{ ok=1;
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x; %ok2=ok;
}
 P0           | P1           | P2                 ;
 MOV R0,#1    | LDR R0,[%x1] | LDREX R0,[%y2]     ;
 STR R0,[%x0] | DMB          | STREX %T2,R0,[%y2] ;
              | MOV R1,#1    | CMP %T2,#0         ;
              | STR R1,[%y1] | BNE Fail2          ;
              |              | CMP R0,R0          ;
              |              | BNE LC00           ;
              |              | LC00:              ;
              |              | LDREX R1,[%x2]     ;
              |              | B Exit2            ;
              |              | Fail2:             ;
              |              | MOV R2,#0          ;
              |              | STR R2,[%ok2]      ;
              |              | Exit2:             ;
Observed
    1:R0=1; 2:R0=1; 2:R1=0; ok=1; y=1;