Executions for behaviour:
"0:R0=0 ; 1:R0=1 ; 1:R2=0 ; 2:R0=1 ; 2:R2=0 ; ok=1 ; x=1 ; y=1"
ARM WRC+dataaa+addrra+A
"RfeAA DpDatadWAA RfeAR DpAddrdRRA FreAA"
Cycle=RfeAA DpDatadWAA RfeAR DpAddrdRRA FreAA
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=RfeAA DpDatadWAA RfeAR DpAddrdRRA FreAA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
P0 | P1 | P2 ;
MOV %T3,#1 | LDREX R0,[%x1] | LDREX R0,[%y2] ;
LDREX R0,[%x0] | STREX %T2,R0,[%x1] | EOR R1,R0,R0 ;
STREX %T2,%T3,[%x0] | CMP %T2,#0 | ADD %T1,R1,%x2 ;
CMP %T2,#0 | BNE Fail1 | LDREX R2,[%T1] ;
BNE Fail0 | EOR R1,R0,R0 | STREX %T2,R2,[%T1] ;
B Exit0 | ADD R1,R1,#1 | CMP %T2,#0 ;
Fail0: | LDREX R2,[%y1] | BNE Fail2 ;
MOV R1,#0 | STREX %T2,R1,[%y1] | B Exit2 ;
STR R1,[%ok0] | CMP %T2,#0 | Fail2: ;
Exit0: | BNE Fail1 | MOV R3,#0 ;
| B Exit1 | STR R3,[%ok2] ;
| Fail1: | Exit2: ;
| MOV R3,#0 | ;
| STR R3,[%ok1] | ;
| Exit1: | ;
Observed
0:R0=0; 1:R0=1; 1:R2=0; 2:R0=1; 2:R2=0; ok=1; x=1; y=1;