Test WRC+ctrlisb+ctrlisbra+A

Executions for behaviour: "0:R0=0 ; 1:R0=1 ; 2:R0=1 ; 2:R1=0 ; ok=1 ; x=1"

ARM WRC+ctrlisb+ctrlisbra+A
"RfeANa DpCtrlIsbdW RfeNaR DpCtrlIsbdRRA FreAA"
Cycle=RfeNaR DpCtrlIsbdRRA FreAA RfeANa DpCtrlIsbdW
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=RfeANa DpCtrlIsbdW RfeNaR DpCtrlIsbdRRA FreAA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y;
%y2=y; %x2=x; %ok2=ok;
}
 P0                  | P1           | P2                 ;
 MOV %T3,#1          | LDR R0,[%x1] | LDREX R0,[%y2]     ;
 LDREX R0,[%x0]      | CMP R0,R0    | CMP R0,R0          ;
 STREX %T2,%T3,[%x0] | BNE LC00     | BNE LC01           ;
 CMP %T2,#0          | LC00:        | LC01:              ;
 BNE Fail0           | ISB          | ISB                ;
 B Exit0             | MOV R1,#1    | LDREX R1,[%x2]     ;
 Fail0:              | STR R1,[%y1] | STREX %T2,R1,[%x2] ;
 MOV R1,#0           |              | CMP %T2,#0         ;
 STR R1,[%ok0]       |              | BNE Fail2          ;
 Exit0:              |              | B Exit2            ;
                     |              | Fail2:             ;
                     |              | MOV R2,#0          ;
                     |              | STR R2,[%ok2]      ;
                     |              | Exit2:             ;
Observed
    0:R0=0; 1:R0=1; 2:R0=1; 2:R1=0; ok=1; x=1;