Test WRC+ctrlana+dmbra+A

Executions for behaviour: "0:R0=0 ; 1:R0=1 ; 2:R0=1 ; 2:R1=0 ; ok=1 ; x=1"

ARM WRC+ctrlana+dmbra+A
"RfeAA DpCtrldWANa RfeNaR DMBdRRRA FreAA"
Cycle=RfeNaR DMBdRRRA FreAA RfeAA DpCtrldWANa
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=RfeAA DpCtrldWANa RfeNaR DMBdRRRA FreAA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0                  | P1                 | P2                 ;
 MOV %T3,#1          | LDREX R0,[%x1]     | LDREX R0,[%y2]     ;
 LDREX R0,[%x0]      | STREX %T2,R0,[%x1] | DMB                ;
 STREX %T2,%T3,[%x0] | CMP %T2,#0         | LDREX R1,[%x2]     ;
 CMP %T2,#0          | BNE Fail1          | STREX %T2,R1,[%x2] ;
 BNE Fail0           | CMP R0,R0          | CMP %T2,#0         ;
 B Exit0             | BNE LC00           | BNE Fail2          ;
 Fail0:              | LC00:              | B Exit2            ;
 MOV R1,#0           | MOV R1,#1          | Fail2:             ;
 STR R1,[%ok0]       | STR R1,[%y1]       | MOV R2,#0          ;
 Exit0:              | B Exit1            | STR R2,[%ok2]      ;
                     | Fail1:             | Exit2:             ;
                     | MOV R2,#0          |                    ;
                     | STR R2,[%ok1]      |                    ;
                     | Exit1:             |                    ;
Observed
    0:R0=0; 1:R0=1; 2:R0=1; 2:R1=0; ok=1; x=1;