Test WRC+ctrl+addrra+A

Executions for behaviour: "0:R0=0 ; 1:R0=1 ; 2:R0=1 ; 2:R2=0 ; ok=1 ; x=1"

ARM WRC+ctrl+addrra+A
"RfeANa DpCtrldW RfeNaR DpAddrdRRA FreAA"
Cycle=RfeNaR DpAddrdRRA FreAA RfeANa DpCtrldW
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=RfeANa DpCtrldW RfeNaR DpAddrdRRA FreAA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y;
%y2=y; %x2=x; %ok2=ok;
}
 P0                  | P1           | P2                 ;
 MOV %T3,#1          | LDR R0,[%x1] | LDREX R0,[%y2]     ;
 LDREX R0,[%x0]      | CMP R0,R0    | EOR R1,R0,R0       ;
 STREX %T2,%T3,[%x0] | BNE LC00     | ADD %T1,R1,%x2     ;
 CMP %T2,#0          | LC00:        | LDREX R2,[%T1]     ;
 BNE Fail0           | MOV R1,#1    | STREX %T2,R2,[%T1] ;
 B Exit0             | STR R1,[%y1] | CMP %T2,#0         ;
 Fail0:              |              | BNE Fail2          ;
 MOV R1,#0           |              | B Exit2            ;
 STR R1,[%ok0]       |              | Fail2:             ;
 Exit0:              |              | MOV R3,#0          ;
                     |              | STR R3,[%ok2]      ;
                     |              | Exit2:             ;
Observed
    0:R0=0; 1:R0=1; 2:R0=1; 2:R2=0; ok=1; x=1;