Test S+poaa+ctrlisbrna

Executions for behaviour: "0:R0=1 ; 0:R1=0 ; 1:R0=1 ; ok=1 ; x=2 ; y=1"

ARM S+poaa+ctrlisbrna
"PodWWAA RfeAR DpCtrlIsbdWRNa WseNaA"
Cycle=RfeAR DpCtrlIsbdWRNa WseNaA PodWWAA
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=PodWWAA RfeAR DpCtrlIsbdWRNa WseNaA
{ ok=1;
%x0=x; %y0=y; %ok0=ok;
%y1=y; %x1=x;
}
 P0                  | P1             ;
 MOV %T3,#2          | LDREX R0,[%y1] ;
 LDREX R0,[%x0]      | CMP R0,R0      ;
 STREX %T2,%T3,[%x0] | BNE LC00       ;
 CMP %T2,#0          | LC00:          ;
 BNE Fail0           | ISB            ;
 MOV %T3,#1          | MOV R1,#1      ;
 LDREX R1,[%y0]      | STR R1,[%x1]   ;
 STREX %T2,%T3,[%y0] |                ;
 CMP %T2,#0          |                ;
 BNE Fail0           |                ;
 B Exit0             |                ;
 Fail0:              |                ;
 MOV R2,#0           |                ;
 STR R2,[%ok0]       |                ;
 Exit0:              |                ;
Observed
    0:R0=1; 0:R1=0; 1:R0=1; ok=1; x=2; y=1;