Test RWC+poar+dmbnaa+A

Executions for behaviour: "0:R0=0 ; 1:R0=1 ; 1:R1=0 ; 2:R1=0 ; ok=1 ; x=1"

ARM RWC+poar+dmbnaa+A
"RfeAA PodRRAR FreRNa DMBdWRNaA FreAA"
Cycle=RfeAA PodRRAR FreRNa DMBdWRNaA FreAA
Prefetch=1:x=F,1:y=T,2:y=F,2:x=T
Com=Rf Fr Fr
Orig=RfeAA PodRRAR FreRNa DMBdWRNaA FreAA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0                  | P1                 | P2                 ;
 MOV %T3,#1          | LDREX R0,[%x1]     | MOV R0,#1          ;
 LDREX R0,[%x0]      | STREX %T2,R0,[%x1] | STR R0,[%y2]       ;
 STREX %T2,%T3,[%x0] | CMP %T2,#0         | DMB                ;
 CMP %T2,#0          | BNE Fail1          | LDREX R1,[%x2]     ;
 BNE Fail0           | LDREX R1,[%y1]     | STREX %T2,R1,[%x2] ;
 B Exit0             | B Exit1            | CMP %T2,#0         ;
 Fail0:              | Fail1:             | BNE Fail2          ;
 MOV R1,#0           | MOV R2,#0          | B Exit2            ;
 STR R1,[%ok0]       | STR R2,[%ok1]      | Fail2:             ;
 Exit0:              | Exit1:             | MOV R2,#0          ;
                     |                    | STR R2,[%ok2]      ;
                     |                    | Exit2:             ;
Observed
    0:R0=0; 1:R0=1; 1:R1=0; 2:R1=0; ok=1; x=1;