Executions for behaviour:
"0:R1=0 ; 1:R0=1 ; 1:R1=0 ; ok=0 ; x=1 ; y=1"
ARM MP+dmbnaa+ctrlra
"DMBdWWNaA RfeAR DpCtrldRRA FreANa"
Cycle=RfeAR DpCtrldRRA FreANa DMBdWWNaA
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMBdWWNaA RfeAR DpCtrldRRA FreANa
{ ok=1;
%x0=x; %y0=y; %ok0=ok;
%y1=y; %x1=x; %ok1=ok;
}
P0 | P1 ;
MOV R0,#1 | LDREX R0,[%y1] ;
STR R0,[%x0] | CMP R0,R0 ;
DMB | BNE LC00 ;
MOV %T3,#1 | LC00: ;
LDREX R1,[%y0] | LDREX R1,[%x1] ;
STREX %T2,%T3,[%y0] | STREX %T2,R1,[%x1] ;
CMP %T2,#0 | CMP %T2,#0 ;
BNE Fail0 | BNE Fail1 ;
B Exit0 | B Exit1 ;
Fail0: | Fail1: ;
MOV R2,#0 | MOV R2,#0 ;
STR R2,[%ok0] | STR R2,[%ok1] ;
Exit0: | Exit1: ;
Observed
0:R1=0; 1:R0=1; 1:R1=0; ok=0; x=1; y=1;