Test IRIW+dmbnaa+pora+AA

Executions for behaviour: "0:R0=0 ; 1:R0=1 ; 1:R1=0 ; 2:R0=0 ; 3:R0=1 ; 3:R1=0 ; ok=1 ; x=1 ; y=1"

ARM IRIW+dmbnaa+pora+AA
"RfeANa DMBdRRNaA FreAA RfeAR PodRRRA FreAA"
Cycle=RfeANa DMBdRRNaA FreAA RfeAR PodRRRA FreAA
Prefetch=1:x=F,1:y=T,3:y=F,3:x=T
Com=Rf Fr Rf Fr
Orig=RfeANa DMBdRRNaA FreAA RfeAR PodRRRA FreAA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %ok2=ok;
%y3=y; %x3=x; %ok3=ok;
}
 P0                  | P1                 | P2                  | P3                 ;
 MOV %T3,#1          | LDR R0,[%x1]       | MOV %T3,#1          | LDREX R0,[%y3]     ;
 LDREX R0,[%x0]      | DMB                | LDREX R0,[%y2]      | LDREX R1,[%x3]     ;
 STREX %T2,%T3,[%x0] | LDREX R1,[%y1]     | STREX %T2,%T3,[%y2] | STREX %T2,R1,[%x3] ;
 CMP %T2,#0          | STREX %T2,R1,[%y1] | CMP %T2,#0          | CMP %T2,#0         ;
 BNE Fail0           | CMP %T2,#0         | BNE Fail2           | BNE Fail3          ;
 B Exit0             | BNE Fail1          | B Exit2             | B Exit3            ;
 Fail0:              | B Exit1            | Fail2:              | Fail3:             ;
 MOV R1,#0           | Fail1:             | MOV R1,#0           | MOV R2,#0          ;
 STR R1,[%ok0]       | MOV R2,#0          | STR R1,[%ok2]       | STR R2,[%ok3]      ;
 Exit0:              | STR R2,[%ok1]      | Exit2:              | Exit3:             ;
                     | Exit1:             |                     |                    ;
Observed
    0:R0=0; 1:R0=1; 1:R1=0; 2:R0=0; 3:R0=1; 3:R1=0; ok=1; x=1; y=1;