Test 3.2W+dmb+rfiar-datarna+rfi-data

Executions for behaviour: "1:R0=1 ; 1:R1=2 ; 2:R1=1 ; ok=1 ; x=2 ; y=2 ; z=1"

ARM 3.2W+dmb+rfiar-datarna+rfi-data
"DMBdWW WseNaA RfiAR DpDatadWRNa Wse Rfi DpDatadW Wse"
Cycle=Rfi DpDatadW Wse DMBdWW WseNaA RfiAR DpDatadWRNa Wse
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=W
Com=Ws Ws Ws
Orig=DMBdWW WseNaA RfiAR DpDatadWRNa Wse Rfi DpDatadW Wse
{ ok=1;
%x0=x; %y0=y;
%y1=y; %z1=z; %ok1=ok;
%z2=z; %x2=x;
}
 P0           | P1                  | P2           ;
 MOV R0,#2    | MOV %T3,#2          | MOV R0,#2    ;
 STR R0,[%x0] | LDREX R0,[%y1]      | STR R0,[%z2] ;
 DMB          | STREX %T2,%T3,[%y1] | LDR R1,[%z2] ;
 MOV R1,#1    | CMP %T2,#0          | EOR R2,R1,R1 ;
 STR R1,[%y0] | BNE Fail1           | ADD R2,R2,#1 ;
              | LDREX R1,[%y1]      | STR R2,[%x2] ;
              | EOR R2,R1,R1        |              ;
              | ADD R2,R2,#1        |              ;
              | STR R2,[%z1]        |              ;
              | B Exit1             |              ;
              | Fail1:              |              ;
              | MOV R3,#0           |              ;
              | STR R3,[%ok1]       |              ;
              | Exit1:              |              ;
Observed
    1:R0=1; 1:R1=2; 2:R1=1; ok=1; x=2; y=2; z=1;