Test WRW+WR+poaas

ARM WRW+WR+poaas
"RfeNaA PodRWAA WseAA PodWRAA FreANa"
Cycle=RfeNaA PodRWAA WseAA PodWRAA FreANa
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Ws Fr
Orig=RfeNaA PodRWAA WseAA PodWRAA FreANa
{ ok=1;
%x0=x;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0           | P1                  | P2                  ;
 MOV R0,#1    | LDREX R0,[%x1]      | MOV %T3,#2          ;
 STR R0,[%x0] | STREX %T2,R0,[%x1]  | LDREX R0,[%y2]      ;
              | CMP %T2,#0          | STREX %T2,%T3,[%y2] ;
              | BNE Fail1           | CMP %T2,#0          ;
              | MOV %T3,#1          | BNE Fail2           ;
              | LDREX R1,[%y1]      | LDREX R1,[%x2]      ;
              | STREX %T2,%T3,[%y1] | STREX %T2,R1,[%x2]  ;
              | CMP %T2,#0          | CMP %T2,#0          ;
              | BNE Fail1           | BNE Fail2           ;
              | B Exit1             | B Exit2             ;
              | Fail1:              | Fail2:              ;
              | MOV R2,#0           | MOV R2,#0           ;
              | STR R2,[%ok1]       | STR R2,[%ok2]       ;
              | Exit1:              | Exit2:              ;
Observed
    1:R0=1; 1:R1=0; 2:R0=1; 2:R1=0; ok=1; x=1; y=2;