Test WRW+WR+addr+dmb+A

ARM WRW+WR+addr+dmb+A
"RfeANa DpAddrdW Wse DMBdWR FreNaA"
Cycle=RfeANa DpAddrdW Wse DMBdWR FreNaA
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Ws Fr
Orig=RfeANa DpAddrdW Wse DMBdWR FreNaA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0                  | P1              | P2           ;
 MOV %T3,#1          | LDR R0,[%x1]    | MOV R0,#2    ;
 LDREX R0,[%x0]      | EOR R1,R0,R0    | STR R0,[%y2] ;
 STREX %T2,%T3,[%x0] | MOV R2,#1       | DMB          ;
 CMP %T2,#0          | STR R2,[R1,%y1] | LDR R1,[%x2] ;
 BNE Fail0           |                 |              ;
 B Exit0             |                 |              ;
 Fail0:              |                 |              ;
 MOV R1,#0           |                 |              ;
 STR R1,[%ok0]       |                 |              ;
 Exit0:              |                 |              ;
Observed
    0:R0=0; 1:R0=1; 2:R1=0; ok=1; x=1; y=2;