Test WRW+2W+addrra+poaa

ARM WRW+2W+addrra+poaa
"RfeNaR DpAddrdWRA WseAA PodWWAA WseANa"
Cycle=RfeNaR DpAddrdWRA WseAA PodWWAA WseANa
Prefetch=1:x=F,1:y=W,2:y=F,2:x=W
Com=Rf Ws Ws
Orig=RfeNaR DpAddrdWRA WseAA PodWWAA WseANa
{ ok=1;
%x0=x;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0           | P1                  | P2                  ;
 MOV R0,#2    | LDREX R0,[%x1]      | MOV %T3,#2          ;
 STR R0,[%x0] | EOR R1,R0,R0        | LDREX R0,[%y2]      ;
              | ADD %T1,R1,%y1      | STREX %T2,%T3,[%y2] ;
              | MOV %T3,#1          | CMP %T2,#0          ;
              | LDREX R2,[%T1]      | BNE Fail2           ;
              | STREX %T2,%T3,[%T1] | MOV %T3,#1          ;
              | CMP %T2,#0          | LDREX R1,[%x2]      ;
              | BNE Fail1           | STREX %T2,%T3,[%x2] ;
              | B Exit1             | CMP %T2,#0          ;
              | Fail1:              | BNE Fail2           ;
              | MOV R3,#0           | B Exit2             ;
              | STR R3,[%ok1]       | Fail2:              ;
              | Exit1:              | MOV R2,#0           ;
              |                     | STR R2,[%ok2]       ;
              |                     | Exit2:              ;
Observed
    1:R0=1; 1:R2=0; 2:R0=0; 2:R1=2; ok=0; x=1; y=2;
and 1:R0=1; 1:R2=0; 2:R0=0; 2:R1=0; ok=0; x=2; y=2;