Test WRR+2W+poaa+poana+A

ARM WRR+2W+poaa+poana+A
"RfeAA PodRRAA FreAA PodWWANa WseNaA"
Cycle=RfeAA PodRRAA FreAA PodWWANa WseNaA
Prefetch=1:x=F,1:y=T,2:y=F,2:x=W
Com=Rf Fr Ws
Orig=RfeAA PodRRAA FreAA PodWWANa WseNaA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0                  | P1                 | P2                  ;
 MOV %T3,#2          | LDREX R0,[%x1]     | MOV %T3,#1          ;
 LDREX R0,[%x0]      | STREX %T2,R0,[%x1] | LDREX R0,[%y2]      ;
 STREX %T2,%T3,[%x0] | CMP %T2,#0         | STREX %T2,%T3,[%y2] ;
 CMP %T2,#0          | BNE Fail1          | CMP %T2,#0          ;
 BNE Fail0           | LDREX R1,[%y1]     | BNE Fail2           ;
 B Exit0             | STREX %T2,R1,[%y1] | MOV R1,#1           ;
 Fail0:              | CMP %T2,#0         | STR R1,[%x2]        ;
 MOV R1,#0           | BNE Fail1          | B Exit2             ;
 STR R1,[%ok0]       | B Exit1            | Fail2:              ;
 Exit0:              | Fail1:             | MOV R2,#0           ;
                     | MOV R2,#0          | STR R2,[%ok2]       ;
                     | STR R2,[%ok1]      | Exit2:              ;
                     | Exit1:             |                     ;
Observed
    0:R0=0; 1:R0=1; 1:R1=0; 2:R0=0; ok=1; x=1; y=1;
and 0:R0=1; 1:R0=1; 1:R1=0; 2:R0=0; ok=1; x=2; y=1;
and 0:R0=1; 1:R0=2; 1:R1=0; 2:R0=0; ok=1; x=2; y=1;