Test WRR+2W+dmbrna+poana

ARM WRR+2W+dmbrna+poana
"RfeNaR DMBdRRRNa FreNaA PodWWANa Wse"
Cycle=RfeNaR DMBdRRRNa FreNaA PodWWANa Wse
Prefetch=1:x=F,1:y=T,2:y=F,2:x=W
Com=Rf Fr Ws
Orig=RfeNaR DMBdRRRNa FreNaA PodWWANa Wse
{ ok=1;
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x; %ok2=ok;
}
 P0           | P1             | P2                  ;
 MOV R0,#2    | LDREX R0,[%x1] | MOV %T3,#1          ;
 STR R0,[%x0] | DMB            | LDREX R0,[%y2]      ;
              | LDR R1,[%y1]   | STREX %T2,%T3,[%y2] ;
              |                | CMP %T2,#0          ;
              |                | BNE Fail2           ;
              |                | MOV R1,#1           ;
              |                | STR R1,[%x2]        ;
              |                | B Exit2             ;
              |                | Fail2:              ;
              |                | MOV R2,#0           ;
              |                | STR R2,[%ok2]       ;
              |                | Exit2:              ;
Observed
    1:R0=1; 1:R1=0; 2:R0=0; ok=1; x=1; y=1;
and 1:R0=1; 1:R1=0; 2:R0=0; ok=1; x=2; y=1;
and 1:R0=2; 1:R1=0; 2:R0=0; ok=1; x=2; y=1;