Test WRC+poaa+addraa

ARM WRC+poaa+addraa
"RfeNaA PodRWAA RfeAA DpAddrdRAA FreANa"
Cycle=RfeNaA PodRWAA RfeAA DpAddrdRAA FreANa
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=RfeNaA PodRWAA RfeAA DpAddrdRAA FreANa
{ ok=1;
%x0=x;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0           | P1                  | P2                 ;
 MOV R0,#1    | LDREX R0,[%x1]      | LDREX R0,[%y2]     ;
 STR R0,[%x0] | STREX %T2,R0,[%x1]  | STREX %T2,R0,[%y2] ;
              | CMP %T2,#0          | CMP %T2,#0         ;
              | BNE Fail1           | BNE Fail2          ;
              | MOV %T3,#1          | EOR R1,R0,R0       ;
              | LDREX R1,[%y1]      | ADD %T1,R1,%x2     ;
              | STREX %T2,%T3,[%y1] | LDREX R2,[%T1]     ;
              | CMP %T2,#0          | STREX %T2,R2,[%T1] ;
              | BNE Fail1           | CMP %T2,#0         ;
              | B Exit1             | BNE Fail2          ;
              | Fail1:              | B Exit2            ;
              | MOV R2,#0           | Fail2:             ;
              | STR R2,[%ok1]       | MOV R3,#0          ;
              | Exit1:              | STR R3,[%ok2]      ;
              |                     | Exit2:             ;
Observed
    1:R0=1; 1:R1=0; 2:R0=1; 2:R2=0; ok=1; x=1; y=1;