Test WRC+datanaa+ctrlisbrna+A

ARM WRC+datanaa+ctrlisbrna+A
"RfeANa DpDatadWNaA RfeAR DpCtrlIsbdRRNa FreNaA"
Cycle=RfeANa DpDatadWNaA RfeAR DpCtrlIsbdRRNa FreNaA
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=RfeANa DpDatadWNaA RfeAR DpCtrlIsbdRRNa FreNaA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x;
}
 P0                  | P1                 | P2             ;
 MOV %T3,#1          | LDR R0,[%x1]       | LDREX R0,[%y2] ;
 LDREX R0,[%x0]      | EOR R1,R0,R0       | CMP R0,R0      ;
 STREX %T2,%T3,[%x0] | ADD R1,R1,#1       | BNE LC00       ;
 CMP %T2,#0          | LDREX R2,[%y1]     | LC00:          ;
 BNE Fail0           | STREX %T2,R1,[%y1] | ISB            ;
 B Exit0             | CMP %T2,#0         | LDR R1,[%x2]   ;
 Fail0:              | BNE Fail1          |                ;
 MOV R1,#0           | B Exit1            |                ;
 STR R1,[%ok0]       | Fail1:             |                ;
 Exit0:              | MOV R3,#0          |                ;
                     | STR R3,[%ok1]      |                ;
                     | Exit1:             |                ;
Observed
    0:R0=0; 1:R0=1; 1:R2=0; 2:R0=1; 2:R1=0; ok=1; x=1; y=1;