ARM WRC+dataana+dmbaa "RfeNaA DpDatadWANa RfeNaA DMBdRRAA FreANa" Cycle=RfeNaA DMBdRRAA FreANa RfeNaA DpDatadWANa Prefetch=1:x=F,1:y=W,2:y=F,2:x=T Com=Rf Rf Fr Orig=RfeNaA DpDatadWANa RfeNaA DMBdRRAA FreANa { ok=1; %x0=x; %x1=x; %y1=y; %ok1=ok; %y2=y; %x2=x; %ok2=ok; } P0 | P1 | P2 ; MOV R0,#1 | LDREX R0,[%x1] | LDREX R0,[%y2] ; STR R0,[%x0] | STREX %T2,R0,[%x1] | STREX %T2,R0,[%y2] ; | CMP %T2,#0 | CMP %T2,#0 ; | BNE Fail1 | BNE Fail2 ; | EOR R1,R0,R0 | DMB ; | ADD R1,R1,#1 | LDREX R1,[%x2] ; | STR R1,[%y1] | STREX %T2,R1,[%x2] ; | B Exit1 | CMP %T2,#0 ; | Fail1: | BNE Fail2 ; | MOV R2,#0 | B Exit2 ; | STR R2,[%ok1] | Fail2: ; | Exit1: | MOV R2,#0 ; | | STR R2,[%ok2] ; | | Exit2: ; Observed 1:R0=1; 2:R0=1; 2:R1=0; ok=1; x=1; y=1;