Test WRC+dataana+ctrlisbnaa+A

ARM WRC+dataana+ctrlisbnaa+A
"RfeAA DpDatadWANa Rfe DpCtrlIsbdRNaA FreAA"
Cycle=Rfe DpCtrlIsbdRNaA FreAA RfeAA DpDatadWANa
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=RfeAA DpDatadWANa Rfe DpCtrlIsbdRNaA FreAA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0                  | P1                 | P2                 ;
 MOV %T3,#1          | LDREX R0,[%x1]     | LDR R0,[%y2]       ;
 LDREX R0,[%x0]      | STREX %T2,R0,[%x1] | CMP R0,R0          ;
 STREX %T2,%T3,[%x0] | CMP %T2,#0         | BNE LC00           ;
 CMP %T2,#0          | BNE Fail1          | LC00:              ;
 BNE Fail0           | EOR R1,R0,R0       | ISB                ;
 B Exit0             | ADD R1,R1,#1       | LDREX R1,[%x2]     ;
 Fail0:              | STR R1,[%y1]       | STREX %T2,R1,[%x2] ;
 MOV R1,#0           | B Exit1            | CMP %T2,#0         ;
 STR R1,[%ok0]       | Fail1:             | BNE Fail2          ;
 Exit0:              | MOV R2,#0          | B Exit2            ;
                     | STR R2,[%ok1]      | Fail2:             ;
                     | Exit1:             | MOV R2,#0          ;
                     |                    | STR R2,[%ok2]      ;
                     |                    | Exit2:             ;
Observed
    0:R0=0; 1:R0=1; 2:R0=1; 2:R1=0; ok=0; x=1;