Test WRC+dataana+addrrr

ARM WRC+dataana+addrrr
"RfeNaA DpDatadWANa RfeNaR DpAddrdRRR FreRNa"
Cycle=RfeNaA DpDatadWANa RfeNaR DpAddrdRRR FreRNa
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=RfeNaA DpDatadWANa RfeNaR DpAddrdRRR FreRNa
{ ok=1;
%x0=x;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x;
}
 P0           | P1                 | P2             ;
 MOV R0,#1    | LDREX R0,[%x1]     | LDREX R0,[%y2] ;
 STR R0,[%x0] | STREX %T2,R0,[%x1] | EOR R1,R0,R0   ;
              | CMP %T2,#0         | ADD %T1,R1,%x2 ;
              | BNE Fail1          | LDREX R2,[%T1] ;
              | EOR R1,R0,R0       |                ;
              | ADD R1,R1,#1       |                ;
              | STR R1,[%y1]       |                ;
              | B Exit1            |                ;
              | Fail1:             |                ;
              | MOV R2,#0          |                ;
              | STR R2,[%ok1]      |                ;
              | Exit1:             |                ;
Observed
    1:R0=1; 2:R0=1; 2:R2=0; ok=1; x=1;