Test WRC+ctrlisbaa+ctrlisbrna+A

ARM WRC+ctrlisbaa+ctrlisbrna+A
"RfeAA DpCtrlIsbdWAA RfeAR DpCtrlIsbdRRNa FreNaA"
Cycle=RfeAA DpCtrlIsbdWAA RfeAR DpCtrlIsbdRRNa FreNaA
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=RfeAA DpCtrlIsbdWAA RfeAR DpCtrlIsbdRRNa FreNaA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x;
}
 P0                  | P1                  | P2             ;
 MOV %T3,#1          | LDREX R0,[%x1]      | LDREX R0,[%y2] ;
 LDREX R0,[%x0]      | STREX %T2,R0,[%x1]  | CMP R0,R0      ;
 STREX %T2,%T3,[%x0] | CMP %T2,#0          | BNE LC01       ;
 CMP %T2,#0          | BNE Fail1           | LC01:          ;
 BNE Fail0           | CMP R0,R0           | ISB            ;
 B Exit0             | BNE LC00            | LDR R1,[%x2]   ;
 Fail0:              | LC00:               |                ;
 MOV R1,#0           | ISB                 |                ;
 STR R1,[%ok0]       | MOV %T3,#1          |                ;
 Exit0:              | LDREX R1,[%y1]      |                ;
                     | STREX %T2,%T3,[%y1] |                ;
                     | CMP %T2,#0          |                ;
                     | BNE Fail1           |                ;
                     | B Exit1             |                ;
                     | Fail1:              |                ;
                     | MOV R2,#0           |                ;
                     | STR R2,[%ok1]       |                ;
                     | Exit1:              |                ;
Observed
    0:R0=0; 1:R0=1; 1:R1=0; 2:R0=1; 2:R1=0; ok=1; x=1; y=1;