Test WRC+addr+ctrlisbrr+A

ARM WRC+addr+ctrlisbrr+A
"RfeANa DpAddrdW RfeNaR DpCtrlIsbdRRR FreRA"
Cycle=RfeNaR DpCtrlIsbdRRR FreRA RfeANa DpAddrdW
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=RfeANa DpAddrdW RfeNaR DpCtrlIsbdRRR FreRA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0                  | P1              | P2             ;
 MOV %T3,#1          | LDR R0,[%x1]    | LDREX R0,[%y2] ;
 LDREX R0,[%x0]      | EOR R1,R0,R0    | CMP R0,R0      ;
 STREX %T2,%T3,[%x0] | MOV R2,#1       | BNE LC00       ;
 CMP %T2,#0          | STR R2,[R1,%y1] | LC00:          ;
 BNE Fail0           |                 | ISB            ;
 B Exit0             |                 | LDREX R1,[%x2] ;
 Fail0:              |                 |                ;
 MOV R1,#0           |                 |                ;
 STR R1,[%ok0]       |                 |                ;
 Exit0:              |                 |                ;
Observed
    0:R0=0; 1:R0=1; 2:R0=1; 2:R1=0; ok=1; x=1;