Test SB+rfiar-addrrnas

ARM SB+rfiar-addrrnas
"RfiAR DpAddrdRRNa FreNaA RfiAR DpAddrdRRNa FreNaA"
Cycle=RfiAR DpAddrdRRNa FreNaA RfiAR DpAddrdRRNa FreNaA
Prefetch=0:x=F,0:y=T,1:y=F,1:x=T
Com=Fr Fr
Orig=RfiAR DpAddrdRRNa FreNaA RfiAR DpAddrdRRNa FreNaA
{ ok=1;
%x0=x; %y0=y; %ok0=ok;
%y1=y; %x1=x; %ok1=ok;
}
 P0                  | P1                  ;
 MOV %T3,#1          | MOV %T3,#1          ;
 LDREX R0,[%x0]      | LDREX R0,[%y1]      ;
 STREX %T2,%T3,[%x0] | STREX %T2,%T3,[%y1] ;
 CMP %T2,#0          | CMP %T2,#0          ;
 BNE Fail0           | BNE Fail1           ;
 LDREX R1,[%x0]      | LDREX R1,[%y1]      ;
 EOR R2,R1,R1        | EOR R2,R1,R1        ;
 LDR R3,[R2,%y0]     | LDR R3,[R2,%x1]     ;
 B Exit0             | B Exit1             ;
 Fail0:              | Fail1:              ;
 MOV R4,#0           | MOV R4,#0           ;
 STR R4,[%ok0]       | STR R4,[%ok1]       ;
 Exit0:              | Exit1:              ;
Observed
    0:R0=0; 0:R1=1; 0:R3=0; 1:R0=0; 1:R1=1; 1:R3=0; ok=1; x=1; y=1;