ARM S+poana+ctrlisbra "PodWWANa RfeNaR DpCtrlIsbdWRA WseAA" Cycle=RfeNaR DpCtrlIsbdWRA WseAA PodWWANa Prefetch=0:x=F,0:y=W,1:y=F,1:x=W Com=Rf Ws Orig=PodWWANa RfeNaR DpCtrlIsbdWRA WseAA { ok=1; %x0=x; %y0=y; %ok0=ok; %y1=y; %x1=x; %ok1=ok; } P0 | P1 ; MOV %T3,#2 | LDREX R0,[%y1] ; LDREX R0,[%x0] | CMP R0,R0 ; STREX %T2,%T3,[%x0] | BNE LC00 ; CMP %T2,#0 | LC00: ; BNE Fail0 | ISB ; MOV R1,#1 | MOV %T3,#1 ; STR R1,[%y0] | LDREX R1,[%x1] ; B Exit0 | STREX %T2,%T3,[%x1] ; Fail0: | CMP %T2,#0 ; MOV R2,#0 | BNE Fail1 ; STR R2,[%ok0] | B Exit1 ; Exit0: | Fail1: ; | MOV R2,#0 ; | STR R2,[%ok1] ; | Exit1: ; Observed 0:R0=0; 1:R0=1; 1:R1=0; ok=0; x=2; and 0:R0=1; 1:R0=1; 1:R1=0; ok=1; x=2;