Test S+poana+addrnaa

ARM S+poana+addrnaa
"PodWWANa Rfe DpAddrdWNaA WseAA"
Cycle=Rfe DpAddrdWNaA WseAA PodWWANa
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=PodWWANa Rfe DpAddrdWNaA WseAA
{ ok=1;
%x0=x; %y0=y; %ok0=ok;
%y1=y; %x1=x; %ok1=ok;
}
 P0                  | P1                  ;
 MOV %T3,#2          | LDR R0,[%y1]        ;
 LDREX R0,[%x0]      | EOR R1,R0,R0        ;
 STREX %T2,%T3,[%x0] | ADD %T1,R1,%x1      ;
 CMP %T2,#0          | MOV %T3,#1          ;
 BNE Fail0           | LDREX R2,[%T1]      ;
 MOV R1,#1           | STREX %T2,%T3,[%T1] ;
 STR R1,[%y0]        | CMP %T2,#0          ;
 B Exit0             | BNE Fail1           ;
 Fail0:              | B Exit1             ;
 MOV R2,#0           | Fail1:              ;
 STR R2,[%ok0]       | MOV R3,#0           ;
 Exit0:              | STR R3,[%ok1]       ;
                     | Exit1:              ;
Observed
    0:R0=0; 1:R0=1; 1:R2=0; ok=0; x=2;
and 0:R0=1; 1:R0=1; 1:R2=0; ok=1; x=2;